1. Field
Aspects of embodiments of the present invention are directed toward methods for addressing high capacity SDRAM-like memory without increasing pin cost or pin count.
2. Description of Related Art
In the JEDEC DDR4 SDRAM (double data rate fourth-generation synchronous dynamic random-access memory) standard, there are 3 pins for CID (chip ID, or rank), 4 pins for bank, and 18 (shared) pins for row or column (depending on command). The current pin usage and addressing scheme supports up to 256 GB per DIMM (dual inline memory module, a collection of numerous DRAM chips or other memory chips in a single package) assuming the precise combination of DRAM chip sizes, widths, and organization is selected and assembled (otherwise, a lower-capacity or lower-addressable DIMM results). Module capacity or addressability larger than that is not supported (e.g., the memory would not be addressable even if it could be physically added to the module).